It is common knowledge that Dynamic Random Access Memory (“DRAM”) modules are comprised of capacitive electrical cells that leak their charge out over time. As a result, DRAM cells must be recharged, or “refreshed”, thousands of times per second or they lose their data. Reading from or writing to a DRAM cell refreshes its charge, so a common way of refreshing a DRAM is to read periodically from each cell. This is typically accomplished by only activating each row using Row Address Strobe or RAS. In addition, a DRAM cell controller takes care of scheduling the refresh cycles and making sure that they don't interfere with regular reads and writes. So to keep the data in DRAM module from leaking away, the cell controller periodically sweeps through all of the rows by cycling RAS repeatedly and placing a series of row addresses on the address bus.
Even though the cell controller handles all the refreshes and tries to schedule them for maximum performance, having to go through and refresh each row every few milliseconds can interfere with the performance of reads and writes and thus have a serious negative impact on the performance of the DRAM modules. Clearly, it is beneficial to overall system performance to reduce the amount of time spent refreshing DRAM cells. As used herein, “system performance” takes into account factors including, but not limited to, data bandwidth, latency, overall system power consumption, acoustic noise, and others.
The number of refresh cycles required to refresh an entire DRAM module depends on the number of rows of DRAM cells in that module; the more rows, the greater the number of cycles required to refresh the entire module. Therefore, one manner in which to reduce the amount of time spent refreshing DRAM modules is to reduce the number of rows in the module.
Another manner in which to reduce the amount of time spent refreshing DRAM modules is to adjust the refresh rate; that is, the frequency with which the modules are refreshed. Commonly, there is a feature in the Basic I/O System (“BIOS”) of a computer system that allows a user to set the refresh rate of the DRAM modules. In one embodiment, BIOS supports three different refresh rate settings, as well as an “AUTO” option. If the AUTO option is selected, the BIOS queries the DRAM modules and uses the lowest setting found for maximum compatibility. Optimizing the refresh rate is important, yet difficult. Refreshing too often negatively impacts system performance, as indicated above. In contrast, refreshing too infrequently can result in lost data due to an increase in errors, some of which may be of such a magnitude as to be uncorrectable.
Other system adjustments that can lessen the frequency or magnitude of DRAM errors include increasing the fan speed and migrating data from one memory module to another. Each adjustment, while positively impacting DRAM performance, has a corresponding negative effect on overall system performance. Accordingly, it would be beneficial only to make such adjustments when absolutely necessary.